With regard to a jitter (a temporal irregularity of characteristic instants regulating a unit interval that is a period of a bit state) dominating a bit error rate (BER) representative of the communication quality in a communication system transmitting high-speed serial data, a total jitter at each BER includes a random jitter (RJ) characterized by unbounded stochastic variations and a deterministic jitter (DJ) characterized by a bounded time width P-P value, and the former, i.e., RJ, includes a thermal noise, shot noise, and flicker, while the latter, i.e., DJ, includes a periodical jitter (PD) such as a sinusoidal jitter (SJ), a data-dependent jitter (DDJ) affected by a pulse sequence representative of data contents, and a bounded uncorrelated jitter (BUJ) such as crosstalk.
The data-dependent jitter (DDJ) related to the present invention is known to be caused by a synergetic effect between duty cycle distortion (DCD) causing an irregularity of a reference clock and inter symbol interference (ISI) derived solely from an attribute of a high-speed transmission channel (e.g., “Reduction of BER of serial data by the clock jitter analysis” Agilent Technologies Co., Ltd. ed., February 2007, also published in the web site).
Among the causes of the total jitter at the BER, conventionally, the inter symbol interference (ISI) is an external factor serving as a given condition that is an attribute of a transmission channel from the viewpoint of apparatus design and, therefore, the verification of actual contribution to EBR is of serious concern for ensuring the communication quality.
To comprehend the bit error rate (BER), various bit error rate testers (BERTs) are frequently used and the description of U.S. Pat. No. 7,979,225 discloses a configuration that sends out high-speed serial data pursuant to various test patterns from a pattern generator incorporated in the bit error rate tester (BERT) to an ISI board simulating a high-speed transmission channel, that supplies the serial data taking on a desired amount of DDJ derived from ISI in the ISI board to a devise under test (DUT), and that returns the output of the devise under test (DUT) to a pattern analyzer incorporated in the bit error rate tester (BERT) so as to enable the comprehension of a limit of proper/improper operation by the devise under test (DUT) for the various test patterns in a short period of time.
The description of U.S. Pat. No. 7,272,756 discloses a technique of creating a test bit pattern on the premise of “Common Electrical I/O(CEI)-Electrical and Jitter Interoperability Agreements For 6G+bps and 11G+bps I/O-1A#OIF-CEI-01.0 (Optical Internetworking Forum 2004)” and “ITU-TO.150 section 5.8” used as international standards related to a test pattern for a BER test.
The ISI board simulating a high-speed transmission channel for the high-speed serial data communication as mentioned in the description of U.S. Pat. No. 7,979,225 is marketed under the product name “Differential Isi Board” by Synthesys Research Inc., California, US.
A general configuration of this kind of ISI board is introduced as a conventional technique in the description of U.S. Pat. No. 8,224,613 with reference to FIG. 1.
In general, in the configuration of this kind of ISI board, as depicted in FIG. 9 accompanying the description of this application, a conductor strip (91a) is embedded inside a plate-shaped dielectric substrate (91) with a dielectric of the substrate itself interposed between the conductor strip and a conductor foil (not depicted) covering the entire undersurface of the substrate and extends to draw a line pattern having a constant width in a plane view while another conductor strip (92a) having a length different from the conductor strip (91a) extends to draw a line pattern having a constant width in a plane view, and a further conductor strip (93a) extends to draw a long linear pattern having a constant width with a curved portion corresponding to a bottom portion of a U-shape in a plane view.
In this way, a plurality of types of the conductor strips (91a) (92a) (93a) embedded inside the plate-shaped dielectric substrate (91) is prepared, drawing patterns having a constant width and respective different lengths and shapes.
Both end portions of each of the conductor strips (91a) (92a) (93a) are coupled to, for example, the sub-miniature A connectors and, in FIG. 9, connectors (91c) (91d) (92c) of this type are depicted.
Although each of the conductor strips (91a) (92a) (93a) exhibits the similar function as a coaxial cable and all the strips form a constant characteristic impedance, each of the conductor strips different in length applies a different transmission loss to a high-frequency transmission signal of high-speed serial data on each of the selectively used conductor strips and, therefore, different amounts of ISI are implemented in multiple stages.
Therefore, in the usual manner, an ISI board of this kind is interposed between a pattern generator and a pattern analyzer built in a bit error rate tester (BERT) to introduce a high-frequency output signal of the pattern generator via a coaxial cable to, for example, the connector (91c) selected as a signal input terminal of the ISI board and to derive the high-frequency output signal via another coaxial cable from the connector (91d) at the other end of the conductor strip (91a) corresponding to the connector (91c) on the ISI board, so as to apply a transmission loss set fixedly in advance for a selected conductor strip to the high-frequency signal for high-speed serial data communication on the selected conductor strip (91a), thereby selectively actualizing an amount of ISI set fixedly in advance in multiple stages.
In the case of “Differential Isi Board” of Synthesys Research Inc. described above, nine stages of ISI amounts can be set by using nine types of conductor strip patterns.
In many cases, to handle a pair of differential signals, an ISI board has the conductor strip (91a) etc. each formed as a pair of strips extended in parallel and in close proximity to each other so as to make up a differential transmission channel and the connectors (91c) (91d) etc. in the both end portions of the conductor strips are each disposed as a set of two connectors in each end portion; however, in the description of this application, for the purpose of simplicity and clarification, an ISI board for single ended form transmission are exemplarily illustrated, including the configuration of the conventional example of FIG. 9.
Although discrete ISI amounts for respective preset stages can be set each time a bit error rate (BER) test condition is set, the ISI amount cannot continuously and variably be set in a wide range while immediately reflecting a result of the bit error rate (BER) tests and, therefore, the conventional ISI board has a problem that it is difficult to simulate ISI to which digital data communication is exposed in an actual transmission channel, in other words, “live” ISI.    Nonpatent Literature 1: “Reduction of BER of serial data by the clock jitter analysis” Agilent Technologies Co., Ltd. ed., February 2007 (also published in the web site), pp. 6-9    Patent Document 1: U.S. Pat. No. 7,979,225    Patent Document 2: U.S. Pat. No. 7,272,756    Patent Document 3: U.S. Pat. No. 8,224,613